This invention relates to circuitry for handling communication of digital information to which bits are added periodically for synchronization or the like, and more particularly to an interface that allows conversion from one data width to another.
A communication protocol that is increasingly of interest is known as “64b/66b encoding.” This is a protocol in which 64 bits of data are scrambled (e.g., to achieve balance between the number of binary ones and the numbers of binary zeros that need to be transmitted so that there is no net direct current in the transmission) and two additional bits having one or more particular sequences are transmitted with each 64 bits as synchronization information. Thus for every 64 bits of information that need to be sent, 64 information bits and two SYNC bits are transmitted. The SYNC bits may be the sequence “10” or “01”. Extra bits of this kind may sometimes be referred to herein as “padding.” There also may be similar padded protocols with other numbers of bits, such as 8b/10b encoding.
Serial communication of padded information can be a challenge because of possibly complicated clocking issues. For example, 66 bits of information may need to be transmitted in the time in which the data source produces 64 bits of real data. Similarly, the receiver circuitry needs to receive 66 bits in the time in which it will subsequently pass on the 64 bits of real data in that 66-bit transmission.
Circuitry for solving this problem, and allowing the different data widths to operate at different rates, so that the total number of bits transferred during a single clock cycle matches, is known, and is commonly referred to informally as a “gearbox.”
In a transmitter gearbox, where the larger number of padded bits used for processing must be converted to the smaller number of bits (generally a power of 2 to be compatible with standard serializer-deserializers) for transmission, data handled internally at one width—e.g., 66 bits—are read into the gearbox in “slices” of that width. After a sufficient number of slices have been buffered, a portion of the first slice—with the number of bits in the portion being equal to the second data width—e.g., 64 bits—is read out. Next, the remaining portion of the first slice—in this case, 2 bits—is read, followed by enough—in this case, 62 bits—of the second slice to make up the second width. This continues until eventually an integral number of slices is read, and then the process repeats. The two sides of the gearbox are clocked by different clocks such that the product of each clock and its respective data width results in the same number of bits being transferred in a given time interval.
The process is reversed for the receiver gearbox, where the smaller number (again, generally a power of 2) of received bits must be converted to the larger number of padded bits for processing. Once again, the data are read into the gearbox in slices having a width of the smaller number of bits—e.g., 64 bits. After a sufficient number of slices have been buffered, the first slice is read out along with a portion of the second slice—with the number of bits in the portion being equal to the number of padding bits (in this case, two bits)—to make up the second data width—e.g., 66 bits. Next, the remainder of the second slice—in this case, 62 bits—is read along with a portion—in this case, four bits—of the third slice to make up the second, larger data width—e.g., 66 bits. Next, the remaining portion of the third slice—in this case, 60 bits—is read, followed by enough—in this case, six bits—of the fourth slice to make up the second width. This continues until eventually an integral number of slices is read, and then the process repeats. As above, the two sides of the gearbox are clocked by different clocks such that the product of each clock and its respective data width results in the same number of bits being transferred in a given time interval.
Such arrangements have heretofore been designed for a particular padded protocol—e.g., 64b/66b encoding. However, many padded protocols, requiring different rate conversions, are in use. In a programmable logic device, it would be desirable to be able to support more than one such protocol, with the selection of protocol—and therefore rate conversion—under the programmable control of the user.
Moreover, after rate conversion, a padded protocol receiver must align the data by finding the padding headers. Because different conversions for different padded protocols result in different widths of data, the alignment circuitry also must be able to operate on different widths of data. It would further be desirable to be able to provide such alignment circuitry, capable of operating on different widths of data under programmable control of the user.